1. Field of the Invention
Aspects of the invention relate generally to multiprocessor computer architectures. More particularly, aspects are directed to memory controller configurations for routing data between processors and memory.
2. Description of Related Art
In many computer systems, such as high speed data processing systems, multiple processors are employed. The processors may be arranged in different configurations. For instance, an array of processors may be configured in a mesh or torus architecture. These processors may be interconnected and have access to external memory through one or more memory controllers.
As multiprocessor computer architectures become more and more complex, it becomes increasingly difficult to determine optimal placement of memory controllers in relation to the processors. Improper placement of memory controllers can cause unwanted delays (latency) or other processing issues. Therefore, it is important to properly evaluate multiprocessor architectures and determine effective placement of the memory controllers.
Systems and methods that optimize memory controller placement relative to the processors, thereby improving memory utilization and reducing latency, are provided.